The following tutorial, by Stuart Sutherland of Sutherland HDL, is an updated version of a paper presented at HDLCon in March 2000. It provides an overview of the changes in the Verilog-2001 standard.

Available for All SmartDV Verification IP SAN JOSE, CALIF. –– October 1, 2019 –– SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) ...