EDN

Who is the EDA leader in SystemVerilog simulation? Part 1

A couple of weeks ago, I took a pre-briefing from the folks at Mentor Graphics and Cadence Design Systems on their plans to standardize on a jointly developed common SystemVerilog verification ...
Semiconductor Engineering

Re-using Common Simulation Set-Up Processes To Speed Regression

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And ...
EDN

Injunction may restrict Cadence use of simulation tech

SANTA CRUZ, Calif. — A preliminary injunction obtained by a small EDA vendor may block Cadence Design Systems Inc. from using the mixed-signal Verilog simulation technology obtained in the acquisition ...
Business Wire

Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation With up to 5X Faster Regressions

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence ® Xcelium ™ Logic Simulator has been enhanced with machine learning technology (ML), called ...