IEEE

A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution

Abstract: This article presents design techniques for an energy-efficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput low-latency ...
GitHub

valorisa/socat-1.8.0.1_for_Windows

The procedure for those who want to compile from the source files. Otherwise for the others, there is one ready-made file 'socat-1.8.0.1.7z'. You can download it by ...
GitHub

Using the right Java

Generally you should use Java with the same architecture as your CPU. There are different version requirements for different Minecraft versions. If you don't know ...
IEEE

A 10-bit 1-MS/s Low-Power SAR ADC with an Integrated Buffer in Dual Sample-and-Hold Architecture

Abstract: This paper presents a low-power design of a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an integrated buffer. A dual sample-and-hold architecture is ...