GitHub

A new python native silicion architecture leveraging chiplets and fpga with a unified memory arena

PyNS: Python-Native Silicon PyNS is an experimental open-source architecture designed to execute Python logic directly in silicon. By moving the interpreter, memory management, and garbage collection ...
IEEE

Integrating Verilog Simulation with Python Automation: A ModelSim and Colab Framework for FPGA Design and Analysis

Abstract: Field-Programmable Gate Arrays (FPGAs) are pivotal in modern hardware development, offering a flexible and efficient platform for implementing digital systems. Traditional workflows for FPGA ...
IEEE

An FPGA-Based Event-Driven SNN Accelerator for DVS Applications With Structured Sparsity and Early-Stop

Abstract: This paper proposed an algorithm-hardware co-design of an event-driven spiking neural network (SNN) accelerator for classification tasks of event-based data from dynamic vision sensors (DVS) ...
GitHub

Hardware-accelerated SHA-256 implemented on a PYNQ-Z2 FPGA. Includes custom SystemVerilog IP, AXI4-Lite/DMA integration, and Python/Jupyter interface. Achieves faster hashing ...

This repository contains the full implementation and documentation of a hardware-accelerated SHA-256 hashing engine developed as a final university project. The project leverages the Xilinx PYNQ-Z2 ...