IEEE

A RISC-V-Based High-Throughput Accelerator for Sparse Winograd CNN Inference on FPGA

Abstract: This letter proposes a RISC-V-based accelerator for inferring a model that uses efficient sparse Winograd convolutional neural networks. This accelerator consists of a RISC-V processor ...
GitHub

SAP RDP Integration Accelerator

The SAP Responsible Design and Production (RDP) Integration Accelerator is an ABAP package designed to streamline the integration of SAP RDP with backend ECC systems or older S/4HANA systems. The ...
IEEE

Fast FPGA Accelerator of Graph Cut Algorithm based on Cached Folding Grid Architecture

Abstract: Graph cut algorithms are widely used to solve min-cut/max-flow problems across various optimization applications. A common approach in recent FPGA accelerators of graph cut algorithms is to ...