IEEE

One-Ferroelectric-Tunnel-FET-Based Reconfigurable Logic Gates

Abstract: A novel reconfigurable logic gate (RLG) utilizing one ferroelectric tunnel field-effect transistor (FeTFET) is proposed for the first time. By leveraging the symmetric ambipolar current of ...
IEEE

A Separated Pre-Charge Sense Amplifier With Fast Sensing, Low Power, Small Area, and High Reliability for Hybrid MTJ/CMOS Logic Circuits

Abstract: The use of logic circuits combined with emerging devices has been studied to overcome the limitations of complementary metal-oxide-semiconductor (CMOS) transistors. Among a variety of ...
GitHub

cmos-inverter

This project demonstrates the complete design, layout, simulation, and verification of a **CMOS Inverter** using the **Electric VLSI Design Tool**. This repository contains the design, simulation, and ...
IEEE

CNTFET Based Pulse Implied Binary Edge Activated Flip-Flop Using Transmission Gate Logic for Low Power VLSI Applications

Abstract: The rapid evolution of low-power applications in VLSI design calls for innovative transistor technologies that are capable of meeting stringent energy efficiency requirements. Carbon ...
IEEE

Logic Technology Device Innovations

Abstract: This paper provides a history of transistor innovations extending up to the present time and a look into the future of CMOS logic technology requirements for long-term sustainable growth on ...
IEEE

A Dual Attention KPConv Network Combined With Attention Gates for Semantic Segmentation of ALS Point Clouds

Abstract: Kernel point convolution (KPConv) defines convolutional weights based on Euclidean distances between kernel points and input points and has shown good segmentation results on several ...
IEEE

A 7mW 22 GHz Frequency Divider Chain by 2048 using CML, TSPC and CMOS Logic in 22FDX

Abstract: This paper presents a low-power frequency divider chain with a division ratio of 2048 realized in a 22nm FDSOI CMOS technology. To optimize the power consumption, yet achieve high-speed ...
IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
IEEE

Low-Voltage CMOS Capacitor-Less LDOs: Bulk-Driven Versus Gate-Driven Comparative Study

Abstract: This paper explores the feasibility of a capacitor-less (CL) low-dropout (LDO) regulator to operate efficiently in a low-voltage environment. The CL-LDO ...
IEEE

Cascading Application of all Optical Universal NAND Gate for Implementation of Basic Logic Gates

Abstract: All optical logic gates has been a prime area of research in the past. Several notable attempts have been made and many designs have been proposed. One of the important aspects in the use of ...