Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool ...
Santa Cruz, Calif. — In the 1990s, Elliot Mednick pioneered low-cost Verilog simulation. Now he's made his VeriWell simulator a free, open-source offering available through the Sourceforge Web site.
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