Electronics Weekly

VHDL training course comes with free development board

Esperan is running a series of project-based HDL training courses intended to teach design skills alongside language syntax. As part of the course package the training company is offering a free ...
Electronics Weekly

Christmas offer on VHDL training coures

Training company Esperan has entered into the festive spirit and is offering three of its training courses which take place before Christmas at discounted prices. The five day ‘EXTRA VHDL Application ...
Design-Reuse

Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM

Henderson, NV – January 9, 2012 – Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), ...
Design-Reuse

Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements

Aldec’s Active-HDL™ enables FPGA designers to take full advantage of the many features within the latest revision to VHDL and helps improve design verification efficiency. Henderson, NV – January 20, ...
EDN

VHDL verification tool is open source

An open-source constrained random verification software package that uses VHDL-200 or -2008 is available for download. The free package offers a proven methodology and allows VHDL design and ...