EDN

Microsemi’s Libero SoC v11.7 Software Increases Security, Usability and Efficiency for FPGA Designs, Enabling Faster Time-to-Market

“The release of our Libero SoC v11.7 software offers a significantly improved user experience due to a new and enhanced constraints flow with a new constraints management view, a fully redesigned ...
Business Insider

Microsemi Announces Libero SoC v11.8 Software Providing FPGA Designers Mixed Language Simulation and Best-in-Class Debugging Capabilities

ALISO VIEJO, Calif., April 11, 2017 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, ...
EDN

Design software for SoC FPGAs speeds run-times

Libero SoC v11.4, Microsemi says, makes significant FPGA design productivity gains with runtime improvements of up to 35%. Productivity enhancements are enabled by improved SERDES design wizards, I/O ...
Design-Reuse

Actel Strengthens Libero Integrated Design Environment for Next-Generation FPGA Designs

SUNNYVALE, Calif., February 12, 2003 - Actel Corporation (Nasdaq: ACTL), a supplier of innovative programmable logic solutions, today announced it has enhanced its Actel Liberoâ„¢ integrated design ...
Design-Reuse

Actel Delivers Secure, Comprehensive Design Flow for Complex FPGA Development Using ARM7 Family Processor

Company's Libero IDE Also Bolsters Industry-Leading Static Timing Analysis and I/O Capabilities MOUNTAIN VIEW, Calif., Nov 02, 2005-- Actel Corporation (Nasdaq: ACTL) today unveiled significant new ...
New Electronics

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Microsemi has announced a collaboration with MathWorks to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development ...
Electronic Design

Libero SoC v11.4 Software Improves FPGA Runtime Up To 35%

According to Microsemi, its updated Libero System-On-Chip (SoC) version 11.4 software reduces design flow runtime by up to 35% and timing analysis runtime by 20% for the company’s SmartFusion and ...