The PX1011B is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011B PCI Express PHY is ...

LOS ALTOS, Calif., June 21, 2004 - Rambus Inc. (Nasdaq: RMBS), a leading developer of chip interface products and services, today unveiled its Turbo PCI Express* physical layer (PHY) platform which ...

Silicon-proven PCIe Subsystem Offers High Performance, Low Risk Alternative to Traditional ASIC, FPGA Options Santa Clara, Calif.—ChipX, the Structured ASIC leader, today announced the CX6100 family ...

IP Cores in 65nm, 80nm, 90nm and 130nm Enable Integration of PCI Express, SATA, SAS, Fibre Channel, XAUI and GBe serial interconnects September 20, 2006 – SNOWBUSH microelectronics today announced ...

Designers now have access to silicon and volume production-proven 40-nm G PCI Express Gen1/Gen2 Physical Layer (PHY) intellectual property (IP). The SiPro PCI Express PHY product line is the first ...

CHESTNUT RIDGE, N.Y., Feb. 23, 2021 /PRNewswire/ -- Teledyne LeCroy introduced the CrossSync™ PHY interposers and software options, enabling the first-ever link between an oscilloscope and a protocol ...

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® and interface IP solutions and M31, a global silicon intellectual property (IP) boutique, today announced that their ...

Artisan Components, a provider of physical intellectual property (IP), and United Microelectronics Corporation (UMC), said that the two companies are now focused on the development of a PCI-Express ...

Synopsys has expanded its DesignWare Mixed-Signal intellectual property (MSIP) portfolio with low-power PCI Express, XAUI, and SATA physical layers (PHYs) in the 130- and 90-nm processes. These ...

It takes a lot of technology to enable something like machine learning, and not all of it is as glamorous as neural network architectures and algorithms. Several levels below that is the actual ...