Business Wire

MathWorks Speeds Up FPGA-in-the-Loop Verification

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced new capabilities in HDL Verifier to speed up FPGA-in-the-loop (FIL) verification. The new FIL capabilities enable faster communication with ...
Electronic Design

Mentor Graphics, Mathworks Optimize FPGA Design Flow

Mentor Graphics has upgraded its Precision Synthesis tool to include hardware description language (HDL) generated by MathWorks Simulink HDL Coder. Customers will be able to transfer VHDL and Verilog ...
Business Insider

Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards

ALISO VIEJO, Calif., April 19, 2018 /PRNewswire/ -- Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, ...
Design-Reuse

The MathWorks and Mentor Graphics Outline Joint DO-254 Workflow for Model-Based Design

NATICK, Mass. and WILSONVILLE, Ore.--March 23, 2010--The MathWorks and Mentor Graphics (NASDAQ: MENT) today announced a joint collaboration to provide guidance on an integrated workflow for DO-254 ...
EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...