EDN

Family of low-skew LVCMOS

introducing a new set of LVCMOS clock fanout buffers for computing and communications applications, the AK8180x family. Clock stop control is synchronous to the falling edge of the input clock.
EDN

Low Impedance LVCMOS Buffer

The CDCLVC1310 is a universal input, 10-output, low impedance LVCMOS clock fanout buffer. This device can produce ten low-jitter LVCMOS clock outputs from one of three inputs, whose primary and ...
New Electronics

Ultra-low-jitter family of LVCMOS clock buffers

Integrated Device Technology has unveiled a new family of clock buffers. The 5PB11xx family of LVCMOS fan-out buffers is able to provide low-jitter metrics of sub-50 fsec RMS additive phase jitter ...
Design-Reuse

Bi-Directional LVDS with LVCMOS

BiDirectional LVDS IO circuit combines LVDS driver and receiver circuits to enable a single pair of IO pads to function as a 1.5Gbps bi-directional LV ...
Design-Reuse

One Platform, Five Libraries: Certus Semiconductor's I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies

Ultra-low power I/O library featuring a 1.8V General Purpose Input Output (GPIO) Ultra-low leakage, high-speed flip-chip I/O library featuring 1.8V to 3.3V GPIO The Inline I/O library includes a 1.8V ...