EDN

Test engineers must join ASIC flow early

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...
Design-Reuse

Altera's Structured ASIC Design Flow Now ITAR-Compliant for Military Applications

SAN JOSE, Calif. -- March 12 2007--Altera Corporation (Nasdaq: ALTR) today announced that the U.S. Department of State has certified that the company's HardCopy(R) II structured ASIC design and ...
Design-Reuse

Magma and ChipX Team to Deliver Unified RTL-to-GDSII Design Flow for Structured ASIC Platforms

Magma design flow supports ChipX CX5000 and future structured ASIC architectures SANTA CLARA, Calif., September 14, 2004 - Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of chip design ...
Electronic Design

Digital ICs> ASICs

As more logic and memory are integrated onto ASICs, manufacturers and foundries are shifting from 130- to 90-nm design rules. The smaller transistors possible at 90 nm enable a near-fourfold increase ...
Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...