Forbes

The RISC-V Architecture Secures Smartwatches With Google And Qualcomm

Today, Google and Qualcomm announced an extension of their partnership to bring RISC-V-based systems-on-chips (SoCs) to market with support for Wear OS, a version of Android for smartwatches and ...
Dark Reading

Security Concerns Plague Emerging Chip Architecture

An emerging chip architecture gaining traction in smartphones, automotive technologies, and other electronics may find adoption stymied by security concerns. Using x86 and ARM processors for hardware ...
Electronic Design

Examining the RISC-V Architecture

RISC-V is an open-source instruction set definition managed by RISC-V International. This TechXchange includes content that delves into the architecture and design of a RISC-V processor core. How did ...
Android Police

Android wants to support a promising open-source CPU architecture

Manuel Vonau was Android Police's Google Editor until April 2024, with expertise in Android, Chrome, Pixels, and other Google products. For five years, he covered tech news and reviewed devices after ...
Semiconductor Engineering

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)

A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. “Despite decades of ...
TechSpot

DeepComputing announces new tablet based on the RISC-V architecture

In context: After introducing the world's first RISC-V laptop, DeepComputing is now launching what is expected to be the first fully-fledged mobile platform based on the open ISA. The company is ...